{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1552827348067 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1552827348073 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 17 20:55:47 2019 " "Processing started: Sun Mar 17 20:55:47 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1552827348073 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1552827348073 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off exp030 -c exp030 " "Command: quartus_map --read_settings_files=on --write_settings_files=off exp030 -c exp030" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1552827348073 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1552827349506 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" {  } {  } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "Analysis & Synthesis" 0 -1 1552827349506 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "exp030.v 1 1 " "Found 1 design units, including 1 entities, in source file exp030.v" { { "Info" "ISGN_ENTITY_NAME" "1 exp030 " "Found entity 1: exp030" {  } { { "exp030.v" "" { Text "E:/My_design/exp030/exp030.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1552827386443 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1552827386443 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "exp030 " "Elaborating entity \"exp030\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1552827386590 ""}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "exp030.v(8) " "Verilog HDL Case Statement information at exp030.v(8): all case item expressions in this case statement are onehot" {  } { { "exp030.v" "" { Text "E:/My_design/exp030/exp030.v" 8 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1552827386591 "|exp030"}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1552827387873 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1552827388493 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1552827388493 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "10 " "Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1552827388552 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1552827388552 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1552827388552 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1552827388552 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4815 " "Peak virtual memory: 4815 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1552827388626 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 17 20:56:28 2019 " "Processing ended: Sun Mar 17 20:56:28 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1552827388626 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:41 " "Elapsed time: 00:00:41" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1552827388626 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1552827388626 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1552827388626 ""}